1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a latency control circuit and method using a queuing design method.
2. Description of the Related Art
As the operating frequency of a DDR DRAM increases higher than 800 MHz, the input latency of the DDR DRAM also increases. The input latency includes an additive latency and a write latency. The additive latency represents the number of delayed clock cycles between an external read command, an external write command, or an external address signal and an internal read command signal, an internal write command signal, or an internal address signal, respectively. The additive latency may be set to, for example, three through ten (AL3 through AL10). The write latency represents the number of delayed clock cycles between an address signal input with a write command or write data and an internal address signal or internal write data generated from the address signal or the write data. The write latency may be set to five through eight (WL5 through WL8).
FIG. 1 illustrates a conventional latency control circuit 100. Referring to FIG. 1, the latency control circuit 100 includes first through eighth registers 101 through 108. The first through eighth registers 101 through 108 sequentially shift a received address or command ADDR/CMD in response to a clock signal CLK. An additive latency control signal is generated according to a set additive latency AL. For example, the output of the third register 103 is generated as the additive latency control signal when the additive latency is three (AL3), the output of the fourth register 104 is generated as the additive latency control signal when the additive latency is four (AL4), and the output of the seventh register 107 is generated as the additive latency control signal when the additive latency is seven (AL7). An internal read command signal, an internal write command signal, or an internal address signal is generated according to the additive latency control signal.
The latency control circuit 100 is required for each address ADDR and each command CMD. If the number of additive latencies is ten, the number of write latencies is eight, the total number of addresses including a column address and a bank address is fifteen, and the number of commands /CS, /RAS, /CAS and /WE is four, the total number of registers required for the latency control circuit 100 corresponds to (15+4)*10+15*8=310. As the number of registers increases, the area occupied by the registers increases and routing becomes complicated.
FIG. 2 illustrates another conventional latency control circuit 200. Referring to FIG. 2, the latency control circuit 200 includes first through seventh registers 201 through 207 that sequentially shift a write command WRT in response to an internal clock signal PCLK. The latency control circuit 200 further includes eighth and ninth registers 208 and 209 that shift an address ADDR in response to the write command WRT and the output of the third register 203, respectively. The eighth register 208 latches the address in response to the write command WRT. The ninth register 209 latches the output of the eighth register 208 in response to the output of the third register 203. The eighth register 208 generates a first address signal CAi+1 in response to one of first, second, third, and fourth write latencies WL1/2/3/4. The ninth register 209 generates a second address signal CAi in response to one of fifth, sixth, and seventh write latencies WL5/6/7.
With respect to the operation of a DDR DRAM, a column cycle delay time tCCD represents the number of delayed clock cycles between a write command and a write command. The column cycle delay time tCCD is defined by the number of clock cycles corresponding to half a burst length (BL), that is, BL/2. When the burst length is eight, tCCD corresponds to four clock cycles. To satisfy the tCCD, the latency control circuit 200 requires the eighth and ninth registers 208 and 209. The eighth register 208 stores an address ADDR corresponding to a first write command WRT and generates the first address signal CAi+1 in response to one of the first, second, third, and fourth write latencies WL1/2/3/4. The ninth register 209 stores the address ADDR stored in the eighth register 208 in response to the output of the third register 203 when an address ADDR corresponding to a second write command WRT is input. At this time, the address ADDR corresponding to the second write command WRT is stored in the eighth register 208. The ninth register 209 generates the second address signal CAi in response to one of the fifth, sixth, and seventh write latencies WL5/6/7.
In the latency control circuit 200, however, the address stored in the eighth register 208 is shifted to the ninth register 209 according to the output of the third register 203 even though the second write command is not input to the latency control circuit 200. Accordingly, the latency control circuit 200 has a surplus operation.